The first idea was gloriously strange. At the University of Florida, three future founders imagined a processor that would borrow its structure from the brain. Jack Kendall’s early concept involved a mesh of memristive nanowires, an analog machine meant to perform enormous numbers of matrix operations with very little wasted motion. Gordon Hirsch Wilson and Juan Claudio Nino joined him in turning that idea into Rain Neuromorphics in 2017. It sounded like science fiction. Then they had to make it in silicon.
- Rain AI designed hardware that moves AI arithmetic closer to memory, where the data already sits.
- Its original analog approach gave way to digital SRAM-based compute in memory after two chip tape-outs.
- It offered licensable IP and custom chip development; its own chip was still described as upcoming.
- Later reporting says fundraising trouble led to broad layoffs, followed by an OpenAI purchase of some patents.
That is the arc worth studying. Rain did not just chase a fashionable market. It found a real bottleneck in AI computing: moving numbers between memory and processor can consume time and energy. But a company can be right about the bottleneck and wrong about the first material it chooses to solve it. Silicon has a stern sense of humor.
First, build a brain
Rain entered Y Combinator’s summer 2018 batch and attracted early backing from Sam Altman. Its ambition was analog computation, using physical behavior rather than only conventional digital logic to carry out neural-network work. In 2022 the company announced a $25 million Series A; Epic Venture Partners announced another $8.1 million investment in a Series A extension in 2024. Reuters described its plan as making chips that mimic aspects of the brain, with potential uses for companies running AI algorithms. The money bought engineering time, not a shortcut around physics.
Co-founder Wilson later gave the frankest account of what happened. Rain taped out two chips and concluded that the materials needed for its analog vision were not mature enough. His list of what survived the disappointment is revealing: bring memory and processing together, reduce the classic traffic jam between them, exploit sparsity. The thesis remained. The substrate changed.
Conceptual architecture, not a measured energy comparison.
A different kind of in memory
Rain’s nearer-term answer became digital compute in memory, built around SRAM. Digital circuits sacrifice some of analog’s romance, but they fit a manufacturing world engineers understand. The company described a tile that could be licensed for custom systems on chips, together with software. Its public product page also advertised custom development. The company’s own accelerator chip appeared there as “upcoming.” Those are three different commercial states, and buyers should keep them separate.
The company said the digital tile would serve low-latency, energy-sensitive AI. Its examples ranged from devices to data centers, and its technical page described support for inference and training. It also discussed compact 4-bit and 8-bit matrix arithmetic, a numerical scheme intended to preserve model accuracy, and on-device fine-tuning. These are design goals and company claims. The public record does not turn them into independently established production benchmarks.
“We taped out two chips, and realized that the technology just wasn’t ready.”Gordon Hirsch Wilson, co-founder, describing the analog program
Rain’s distinction was not that it discovered AI needs efficient chips. Every accelerator company knows that. Its bet was on the location of the math: bring operations into the memory structure, then wrap that special-purpose engine in a programmable system. In June 2024 it licensed Andes Technology’s AX45MPV RISC-V vector processor and engaged Andes on integration and instruction customization. A matrix engine is good at matrices. Real models also contain other operators. The RISC-V core was a practical answer to that untidy fact.
What a customer could actually buy
Rain’s likely buyer was another engineering organization: a device maker needing efficient on-device AI, a chip designer building a custom SoC, or an infrastructure team trying to make model serving less power hungry. Those customers do not buy a slogan. They need a part or an IP block that works with their model, their software, their thermal budget, and their manufacturing plan. Rain’s advertised route to revenue was licensing its digital in-memory tile and software, with custom development around it. There is no public count of paying customers or shipped Rain accelerators.
The difference matters most in the company’s famous prospective deal. OpenAI signed a nonbinding letter of intent to spend $51 million on Rain chips if a pilot succeeded, according to later reporting by The Information. It was a conditional plan, not a purchase order and not revenue. The pilot condition was never satisfied; OpenAI did not buy the chips. A large number in a headline can become a mirage if the condition underneath it is left out.
The expensive middle
Rain assembled a serious cast. Kendall brought the founding research vision. In 2024 the company announced former Apple chip engineering leader Jean-Didier Allegrucci and former Meta AI hardware architect Amin Firoozshahian. It had already partnered with Mila in Quebec on learning algorithms. Rain AI UK researchers Kendall and Benjamin Scellier were selected for separate projects in Britain’s ARIA Scaling Compute program. The analog idea had not vanished; it had moved partly into longer-term research while the commercial roadmap took a digital turn.
Yet the middle of a chip company’s life is expensive. Prototype work must become reliable hardware, compilers, customer pilots, and a manufacturing path. The Information reported that Rain struggled to raise funds in 2025 and explored a sale. It reported that nearly all employees were laid off in June of that year, and that OpenAI later bought some Rain patents after declining a broader acquisition. The price of those patents was not disclosed. Rain’s website still describes its planned hardware, but the later reporting makes it misleading to read that page as proof of a live chip business.
The lesson inside the circuit
Rain’s story is useful because its pivot was precise. The team did not throw away the observation that data movement costs money and power. It replaced an immature implementation with one closer to established semiconductor production. Anyone building hard technology can copy that discipline: name the physical constraint, run a real experiment, and let the results revise the roadmap. Then ask a tougher commercial question than “Could a customer want this?” Ask whether the prototype, software, manufacturing, and conditional customer commitment can all become true before the money runs out.
There is a limit to the lesson. Digital compute in memory is no universal escape hatch. It must earn its place on measured power, performance, accuracy, programmability, cost, and yield against GPUs and other accelerators. Some workloads may gain little from the trade. A customer whose model changes often may care more about flexibility than arithmetic density. Rain’s patents may have found a buyer; that alone cannot tell us how its proposed chips would have fared in the market. The striking fact is smaller and sharper: the company changed its mind when the chips told it to. The silicon, as usual, was not impressed by the pitch deck.