Altera gives silicon a second chance

The lid was held on with Scotch tape. In the early days of Altera, engineers needed to open their chip packages, probe the silicon, erase a configuration and try again. A permanently sealed lid would have been inconvenient. So the engineering samples got a temporary one. It was a small accommodation to a large idea: hardware ought to allow a change of mind.

Altera emerged in 1983 from Source III, a consultancy whose work exposed the awkward economics of custom gate arrays. Design tools were difficult. Custom manufacturing masks cost money. Getting a circuit wrong could mean paying to make it again. The founders wanted customers to configure logic after manufacture. In 1984, Altera paired its EP300 reprogrammable device with A+PLUS, a PC-based development system.

Robert Hartmann, a co-founder, later pointed to the irreversibility of older fuse-programmed parts. The early EP300 team recalled that its first silicon worked, although a mask revision preceded production. The useful origin story is the obstacle they had observed in their customers’ work: correcting a decision was too expensive.

“You can’t un-blow a fuse.”

Robert Hartmann · Altera co-founder

A company gets reconfigured

Four decades later, Altera has its own costly sequence of decisions to revise. Intel acquired it in 2015 for approximately $16.7 billion. The business became Intel’s Programmable Solutions Group. In 2024, the Altera name returned. In September 2025, Silver Lake completed its purchase of 51%; Intel retained 49%. The transaction had been announced at an $8.75 billion valuation.

The reset followed difficult results. Intel disclosed $1.54 billion of Altera revenue and a $615 million GAAP operating loss for 2024. Its adjusted operating income was $35 million. Those accounting measures describe different things; neither should disappear from the story. Intel framed the sale around sharper focus, lower expenses and a stronger balance sheet.

Raghib Hussain, previously president of Products and Technologies at Marvell and a co-founder of Cavium, became Altera’s CEO in May 2025. The pitch for independence is practical: programmable logic gets management attention of its own. In September 2026, Altera announced that its parent had confidentially submitted an IPO registration statement. Share count and pricing remained undetermined. A filing is a step, not a completed flotation.

The useful work between machines

An FPGA is a field-programmable gate array. Engineers load a configuration that defines logic, connections and input/output behavior. Instead of merely running another program on a fixed processor architecture, they can arrange hardware around the task. That makes sense when several streams need processing simultaneously, or when a response must arrive predictably.

Consider the ultrasound demonstration announced on October 21, 2026. Yuan’s system combines a Texas Instruments ultrasound evaluation module, a Terasic FPGA sensor-aggregation platform and NVIDIA Holoscan. Altera’s programmable logic helps carry sensor data into GPU processing over a 100G bridge. This is a demonstration of a data path, not evidence of a clinically validated medical product.

Here is Altera’s place in the AI market: collecting, converting, timestamping and moving information so another processor can use it. The FPGA can also perform inference and signal processing. But the bridge itself is valuable. A capable GPU cannot analyze sensor information that has not arrived.

This work has a history. Microsoft’s Catapult project used Altera devices in its exploration of configurable cloud infrastructure. Microsoft reports that FPGA-enabled servers entered Bing and Azure deployments at scale in 2015. More recently, Riverlane validated a quantum error-correction interface example on Agilex 7. Search ranking, ultrasound and quantum control sound unrelated. They share an appetite for carefully designed data movement.

The software is part of the chip

The product ladder follows different constraints. Agilex 3 addresses cost-sensitive embedded designs. Agilex 5 serves midrange systems. Agilex 7 handles demanding compute, memory and connectivity workloads. Agilex 9 Direct RF brings data converters into the package. Established Stratix, Arria, Cyclone and MAX families remain part of the wider portfolio.

Altera sells devices, development kits, software licenses and IP: reusable circuit functions such as interfaces and processing blocks. Quartus Prime turns a design into an implementation, checking placement, routing and timing. Free tiers cover selected devices; the full bill depends on hardware, licenses, IP and engineering effort.

On October 21, Altera announced QuartusIQ, an AI companion intended to help engineers debug designs and resolve timing problems using project context. Availability is planned for October 28 with Quartus Prime Pro 26.3. The announcement addresses a stubborn constraint: configurable silicon still requires people who can design and verify what it should do.

A calendar that runs to 2045

AMD’s FPGA and adaptive SoC portfolio, Lattice and Microchip give buyers alternatives. Altera’s case combines portfolio breadth, its Quartus environment and a company focused on programmable logic. Architecture still comes first. Ordinary software may need only a CPU. A fixed design at very high volume may justify an ASIC’s upfront expense and lower unit cost. Flexibility has a price.

For industrial and medical manufacturers, the calendar matters too. Altera plans availability through 2045 for selected Agilex, MAX 10 and Cyclone V families. The extension excludes Agilex 7 devices with integrated HBM2E memory and carries supply-related conditions. Avoiding an unwanted redesign can matter as much as a faster benchmark.

The idea readers can borrow is precise: find the expensive commitment customers wish they could revise. Give them a way to revise it, and the tools to do so reliably. Altera began with the cost of changing a circuit. Its next chapter depends on making that freedom worth buying again.