He spent 20 years building chips that made storage faster. Then he decided the real problem wasn't the drive - it was where the compute sat relative to the data. ScaleFlux is what happened next.
There's a specific moment in 2008 that tells you something about Hao Zhong. While at LSI Corporation, he and his team shipped the industry's first 40nm LDPC read channel chip. LDPC - Low-Density Parity-Check - is the error-correction mathematics that makes modern flash storage reliable enough to trust. It's unglamorous, deeply technical work. The kind that doesn't make headlines but makes everything else possible.
That's the thread running through his entire career: finding the unglamorous technical bottleneck that everyone else has decided to live with, then doing something about it.
After LSI came SandForce, an SSD controller startup that pushed flash storage into serious enterprise territory. Then Fusion-io, where Zhong led the flash memory technology team and pushed LDPC into their PCIe SSD line - the same drives that companies like Apple and Facebook used to accelerate databases before NVMe became the standard. He joined Fusion-io in 2012 and left in 2014 with a clear thesis about where storage had gone wrong.
"We encapsulate all the complexity under the NVMe device protocol. So there's no change for any application."- Hao Zhong, CEO of ScaleFlux
The thesis was this: every time you write data to an SSD, the drive's firmware does more work than you think. Write amplification, garbage collection, wear leveling - the device is burning endurance and burning cycles on bookkeeping that, in principle, could be done smarter. And if you put a proper processor inside the drive itself, not just a simple controller but a real compute-capable SoC, you could do far more: compress data before it lands on flash, inline, transparently, without touching a single line of application code.
In October 2014, Zhong co-founded ScaleFlux with three colleagues: Tong Zhang (who also holds a professorship at Rensselaer Polytechnic Institute, Zhong's own PhD alma mater), Yang Liu as Chief Architect, and Fei Sun as VP Engineering. The company's first product category - Computational Storage Drives - would take several years and multiple funding rounds to reach market. That's the timeline of semiconductor hardware. You don't iterate in weeks.
"For the random write we have from over 200 per cent to as much as 600 per cent improvement."- Hao Zhong, on CSD performance gains
The flagship product, the CSD series, uses ScaleFlux's Write Reduction Technology (WRT) - in-line hardware compression that reduces the amount of data actually written to NAND flash. The results are measurable and specific. Standard NVMe drives deliver around 34,000 random write IOPS in database workloads. ScaleFlux CSDs deliver 180,000. That's not a benchmark footnote; it's a 5x multiplier on workloads where storage is the bottleneck.
Effective capacity increases by 4x through compression. Endurance improves by 3-6x because fewer bytes land on the flash cells. And the economics follow: ScaleFlux claims their drives deliver better-than-commodity pricing at significantly better-than-commodity performance. The punchline is that the drive looks like a standard NVMe device to any host operating system. No driver changes, no application rewrites, no complexity pushed up the stack.
The company kept building. By late 2020 they had closed a Series C round. By 2024, revenue in the first half of the year had already exceeded any previous full-year total. The CSD 5000 series drove customer acquisition and repeat orders at a rate that marked a clear inflection.
Then came the expansion beyond storage. ScaleFlux began shipping NVMe SSD controllers - the FC5116 and FC5104 - with Caliptra security integration and advanced power efficiency for OEM customers who want the silicon without the full drive. And then came the MC500: a CXL 3.1 memory controller supporting DDR4 and DDR5 configurations up to 1TB. Computational storage was the beachhead; memory disaggregation is the next front.
CXL - Compute Express Link - is the interconnect protocol that allows CPUs, GPUs, and memory to share a common address space across PCIe. For AI inference workloads that need enormous amounts of low-latency memory but can't afford the cost of server DRAM at scale, CXL memory expansion is becoming a serious option. ScaleFlux is positioned for that transition with a controller that was built from the ground up rather than acquired.
"They have 34,000 random write IOPS. We can pump it up to all the way to 180,000."- Hao Zhong, on computational storage vs. standard NVMe
Zhong has spoken openly about the challenge of building a hardware company in the United States as a founder with Chinese roots. In a 2025 interview with Sheffield Haworth, he discussed the specific pressure of US-Sino relations on investment and customer relationships in the semiconductor space - a dynamic that shapes which investors will write checks, which markets are accessible, and which supply chain partners are available. It's a constraint that software founders rarely have to map onto their roadmaps.
ScaleFlux now has 210 employees and continues to expand its sales force across the US and Asia. The company appeared at GTC San Jose in March 2026 alongside the GPU computing industry's biggest names - a signal about where ScaleFlux sees its future customers. AI training and inference workloads are consuming storage infrastructure at a rate that makes the computational storage thesis more compelling each year. Every model checkpoint, every training dataset, every inference log is data at rest that needs to move fast and store dense.
In 2025, ScaleFlux was recognized on the MES Midmarket 100 list, which tracks high-growth companies in the middle market. Zhong also spoke at the GSA Awards 2025 on the pivotal role of storage in modern data infrastructure - a theme that would have seemed narrow ten years ago and now lands differently in a world where GPUs are the bottleneck and everything else is trying to keep up.
His PhD work at Rensselaer Polytechnic Institute - the same institution where his co-founder Tong Zhang still holds a faculty position - gave him the theoretical grounding for the error-correction work he'd do at LSI and Fusion-io. The arc from PhD to chip architect to engineering director to co-founder is a specific Silicon Valley pattern: deep technical expertise that accumulates across companies until the combination of knowledge, timing, and co-founder chemistry makes a new company the logical next move.
The data pipeline is being rethought from the inside out. Offloading compute from the CPU to the storage layer isn't a new idea - it's been debated in storage architecture circles for decades. What Zhong did was build the chip that makes it real at a price point that enterprise customers will actually pay.
"We encapsulate all the complexity under the NVMe device protocol. So there's no change for any application."
On product design philosophy"We can improve the endurance by three to six times. The performance increase depends on whether it is a read or write."
On CSD performance metrics - Blocks and Files, 2021"For the random write we have from over 200 per cent to as much as 600 per cent improvement."
On write performance gains"They have 34,000 random write IOPS. We can pump it up to all the way to 180,000."
On competitive benchmarksHis PhD institution - Rensselaer Polytechnic Institute - is also where ScaleFlux co-founder and Chief Scientist Tong Zhang still holds a faculty position.
ScaleFlux's CSD 3000 and 5000 drives look identical to standard NVMe devices from the host OS. The entire compute-in-storage magic is invisible to software.
The MC500 CXL controller supports configurations up to 1TB of DDR4/DDR5 memory - targeting the AI inference market where memory capacity is the binding constraint.
ScaleFlux has 27 investors including major Asian tech conglomerates. Zhong has discussed the complexity of US-Sino relations on fundraising and customer access in the semiconductor space.
The company's patent portfolio covers storage security, self-managed DRAM energy, storage system scalability, and lossless compression algorithms - a broad moat built over a decade.
Hao Zhong founded ScaleFlux alongside three co-founders with backgrounds that read like a storage technology who's-who. Tong Zhang, Chief Scientist, holds a faculty position at Rensselaer Polytechnic Institute and brings deep academic expertise in flash memory systems and error correction - the theoretical backbone of what ScaleFlux's chips do. Yang Liu, Chief Architect, brings hardware design experience that made the SoC a reality. Fei Sun, VP Engineering, has held the execution thread across product generations.
The combination of industry experience (Zhong and Sun), academic depth (Zhang), and architecture expertise (Liu) is the specific mix that semiconductor startups need. You can't buy this kind of co-founder complementarity; it accumulates from years of working in adjacent roles at overlapping companies.
GSA AWARDS 2025 - Hao Zhong on the pivotal role of storage in modern data infrastructure