The modern AI chip has a peculiar problem: it can calculate faster than it can be fed. Add CPUs, GPUs, neural processors, caches, high-bandwidth memory and I/O blocks, and the machine begins to resemble a city designed by brilliant landlords who forgot to agree on roads. Every block may be impressive. The system still stalls when too many bytes reach the same intersection.
Baya Systems lives at that intersection. Founded in 2023 by semiconductor architect Sailesh Kumar, the Santa Clara company develops the connective tissue inside systems-on-chip and multi-chiplet packages. Its fabric moves data among compute engines, memory and interfaces. Its companion software lets an architect model that traffic, choose a topology, tune quality of service and test performance while changes are still inexpensive.
This is not a consumer AI story. There is no chatbot and no glowing device. Baya sells business-to-business intellectual property and design tools to the teams that make the silicon underneath data centers, automotive systems, edge machines and high-performance computers. The most useful way to understand it is simple: WeaveIP is the road network; WeaverPro is the traffic simulator and planning desk.
The chip has become a traffic problem
For decades, performance gains were narrated through transistor counts and processor speed. AI changed the emphasis. Accelerators can perform vast numbers of operations, but their useful work depends on getting the right model weights and activations to the right engine at the right moment. Chiplets add flexibility by breaking a giant design into reusable dies, yet every new boundary introduces another route, protocol and potential choke point.
In a 2026 announcement with connectivity developer Kandou AI, the companies framed the imbalance sharply: compute had scaled 60,000-fold over two decades while interconnect had improved only 30-fold. Those figures are their comparison, not a universal benchmark, but the gap explains the market. The expensive arithmetic units can sit idle because the plumbing cannot keep pace.
Baya's answer begins before hardware description code is fixed. WeaverPro accepts workload information and lets teams explore cache hierarchies, fabric configurations and chiplet partitioning. FabricStudio supports static analysis and cycle-accurate simulation; CacheStudio examines how memory and caches behave. SystemC and Python interfaces allow the tools to join an existing development environment. Once an architecture is chosen, the flow can generate a physically aware, correct-by-construction implementation using WeaveIP components.
The tiled implementation approach is a genuine competitive advantage for teams working at our pace.Srujan Linga, Kandou AI co-founder and CEO
One transport, several kinds of traffic
Traditional chip projects often accumulate separate interconnects: one coherent path for processors and caches, another non-coherent network for accelerators or I/O, and custom links for unusual blocks. Baya argues that this fragmentation consumes silicon area, power and engineering time. WeaveIP instead uses a shared transport architecture that can carry different protocols and be configured around a workload.
That architecture is the core distinction Baya claims against established network-on-chip vendors and in-house designs. Arteris, Synopsys and Arm all offer serious interconnect alternatives. Large chip companies can also build their own. Baya's wager is not that rivals lack fabric, but that a linked software-and-IP loop can expose performance trade-offs earlier, support protocol flexibility, and scale from one die to many without forcing a redesign at every boundary.
WeaverPro
Architecture exploration and performance modeling, from workload analysis to post-silicon tuning.
WeaveIP
Reusable fabric components built on a common transport for coherent, non-coherent and custom traffic.
NeuraScale
Non-blocking switching for AI scale-up and scale-out systems using UALink, Ultra Ethernet or AMBA ports.
Studios
FabricStudio shapes interconnect; CacheStudio tests memory hierarchy and system partitioning.
The product is also the insurance policy
A software bug can be patched after launch. A silicon error can mean new masks, lost quarters and a bruising re-spin. Baya's business case is therefore partly about risk. Teams can simulate real workloads, inspect congestion, reserve bandwidth for critical traffic and check whether latency targets survive contention. The fabric includes quality-of-service controls, reliability features, virtual channels and protocol adaptation. “Deadlock-free” sounds like an obscure checkbox until two parts of a chip wait forever for each other.
The commercial model follows familiar semiconductor economics. Customers license IP that becomes part of a chip and use enterprise software to configure and validate it. Pricing and revenue are private. The value proposition is measured against engineers' time, silicon area, power consumption and the cost of missing a product window. Baya is not merely selling a block; it is selling a repeatable path from architectural question to implemented fabric.
Customers as proof, partners as distribution
Semiconductor IP companies rarely grow alone. Their products must meet processors, memory controllers, physical links, electronic-design tools and foundry constraints. Baya has treated that ecosystem as part of the offer. Blue Cheetah pairs its die-to-die physical layer with Baya's digital fabric. Aion Silicon combines WeaverPro and WeaveIP with architecture, integration and implementation services. Andes Technology connects its RISC-V processor IP into the flow and named Baya its 2025 Partner of the Year.
The customer list is short but specific. Tenstorrent was disclosed as an early licensee and later demonstrated WeaveIP interoperability with its TT-Ascalon processors. Openchip licensed Baya's NoC and data-movement platform in 2026. Kandou AI is deploying WeaveIP and WeaverPro for a 448-gigabit copper-connectivity platform. Each relationship occupies a different layer, suggesting Baya wants to be neutral connective infrastructure rather than a competing processor.
Investors have reinforced that strategy. Maverick Silicon led the January 2025 Series B of more than $36 million. Synopsys made a strategic investment, while Matrix Partners and Intel Capital reinvested. The money was earmarked for operational expansion and faster deployment of the portfolio. The company later opened a United Kingdom office and continued hiring across California, Texas, Bengaluru and the UK.
Data movement between compute, I/O, memory and caches is emerging as a fundamental challenge in scaling AI systems efficiently.Sailesh Kumar, founder and CEO
A bird's nest, translated into silicon
The name supplies an unusually apt bit of semiconductor whimsy. A baya weaver builds a strong, lightweight nest by binding different materials into one structure. Baya Systems wants to do the same with compute, communications, memory and I/O. Its product names - WeaveIP, WeaverPro, FabricStudio - carry the metaphor almost to the point of embroidery.
The company itself is built from familiar fibers. Kumar previously founded NetSpeed Systems, another network-on-chip company, and stayed after Intel acquired it in 2018. Baya's leadership includes veterans whose public biographies span Arm, AMD, Apple, Tesla, Meta, Intel and Huawei. Its careers material emphasizes ownership, collaborative argument and learning between experienced architects and newer engineers. That is less decorative than it sounds: interconnect problems sit between specialties, so a team organized into hard silos would recreate the product problem inside the company.
Baya now sits in the semiconductor IP layer between chip architecture and physical implementation, adjacent to electronic-design automation but tied directly to what ships in silicon. Its opportunity expands as systems become heterogeneous and chiplet-based. Its challenge is equally clear: established competitors have long customer histories, broad portfolios and silicon-proven credibility accumulated over many designs.
The startup's progress so far offers evidence without closing the case. It has been named to the 2025 EE Times Silicon 100, received Frost & Sullivan's interconnect innovation award, won an EPDT product award and earned ISO 9001:2015 certification. More important than plaques are the disclosed licenses and interoperable systems. In semiconductor IP, the most persuasive marketing object is a customer design that works.
What people can actually do with it
For a chip architect, the immediate use is to ask better questions sooner. What happens when a neural engine and CPU compete for the same memory? Which traffic deserves guaranteed service? Should a cache sit on this die or that one? Can a fabric carry a proprietary protocol without duplicating the entire network? How much throughput remains when the floor plan stretches links across a large chip?
WeaverPro turns those questions into models; WeaveIP turns the chosen model into an implementation. NeuraScale extends the logic to switching across clusters of accelerators. If the approach works as intended, customers get fewer late surprises, more reuse across products and a clearer view of performance before tape-out. The end user never sees the fabric. They notice the effect indirectly: an AI system that spends less time waiting for its own data.