Arteris Put a Tiny Internet Inside the Chip - Then Turned the Traffic Jam Into a Business

The small orange square in Arteris's logo is a decent visual joke. The company lives in the squares inside your electronics - processors, memories, neural engines, video blocks - and in the lines between them. Those lines look harmless on a presentation slide. On a real system-on-chip, they are where good architectures go to become late projects.

Arteris licenses the connective tissue. Its network-on-chip, or NoC, intellectual property moves data between components using packet-based routes rather than forcing every block onto one increasingly overloaded bus. Think city streets instead of one colossal hallway. The customer still designs the destination - an automotive processor, AI accelerator, 5G chip, storage controller or industrial device - but Arteris supplies a configurable traffic system and the tools to assemble it.

A network where a bus used to be

The problem grows with success. Add more compute engines, protocols, clock domains and power islands, and a conventional crossbar becomes a thicket of long wires. Engineers can miss timing targets, run into routing congestion, waste die area or burn too much power moving data. Worse, they often discover the physical problem late, when another design iteration is expensive and the manufacturing slot is not politely waiting.

FlexNoC, Arteris's workhorse since 2009, lets teams tailor topology, bandwidth, latency, quality of service and protocol conversion. Ncore handles the harder problem of cache coherence, keeping multiple processors and caches working from a consistent view of memory. CodaCache parks frequently needed data closer to the compute. FlexWay covers smaller designs. None is a magic chip: each is licensed IP that becomes part of the customer's RTL and eventual silicon.

That history matters because interconnect IP is not a download-and-hope purchase. A design team is betting a costly tape-out on behavior under thousands of traffic conditions. Arteris's pitch is partly technical and partly actuarial: its technology has already met many awkward combinations of processors, protocols, foundries and design tools. Customers include AMD, Arm, NXP, Renesas, Samsung Foundry, Mobileye, Bosch and Altera, along with hyperscalers that often prefer not to name what is inside their chips.

“The SoC is not done until the software drivers run.”Richard Weber, founder of Semifore, later acquired by Arteris

The company before the company

Arteris began with a closure. Philippe Boucard, Alain Fanet and César Douady had worked together at Matra, then built network processors at T.Sqware. That company closed in 2002. The three engineers did not discard the networking knowledge. They changed its address.

In Paris in 2003, they started applying packet-network ideas inside silicon. The first product, NoCSolution, shipped in 2006. Texas Instruments licensed it for OMAP processors the next year, providing the kind of production validation a young IP vendor needs more than a clever acronym. FlexNoC followed in 2009 and lowered the adoption barrier. Samsung and Qualcomm became important mobile-era users; Arteris first turned cash-flow positive in 2010 and profitable in 2011.

This is the first thing worth stealing: when a market disappears, inventory the expertise rather than the product. T.Sqware's network processor was gone. The founders' knowledge of distributed communication still had value. They found a smaller physical canvas and a larger eventual problem.

The cost was not just venture money. Staying credible in this market is an R&D habit. Arteris spent $49.9 million on research and development in 2025, roughly 71 percent of that year's $70.6 million revenue. It posted a $34.7 million net loss even as revenue grew. In the second quarter of 2026, revenue reached a record $24.1 million, but the company still reported a $14.1 million net loss. The infrastructure may be reused; keeping it current is not cheap.

Connectivity was a wedge, not the whole workflow

Arteris once looked like a pure NoC company. The modern portfolio says management changed its mind about where the job begins and ends. Buying Magillem's assets in 2020 added software for packaging IP, connecting blocks and managing registers. Acquiring Semifore in 2023 added CSRCompiler, which turns a shared register specification into hardware descriptions, software headers, verification material and documentation.

FlexGen arrived in 2025 to automate more of the NoC itself. Arteris says it can reduce design iteration time by up to 10 times, cut manual adjustments by more than 90 percent, trim wire length by up to 30 percent and reduce latency by up to 10 percent. Those are vendor figures, dependent on the design. The practical change is still notable: topology generation becomes less like artisan tuning and more like software-guided search. AMD licensed FlexGen for next-generation AI chiplets, a strong test of whether that automation survives serious workloads.

Then security moved onto the bill. Arteris closed its $45 million purchase of Cycuity in January 2026. The Radix tools analyze how sensitive information can flow through hardware, from static RTL checks through simulation and emulation. That puts security assurance beside connectivity and integration automation. Arm, already a partner, expanded Radix use across additional CPU programs in July.

Paid before the chip, and sometimes after

Arteris sells negotiated licenses, support, maintenance and professional services. It does not publish a menu price. Some contracts also generate royalties after customers ship production silicon. This gives the business two clocks: fixed revenue around design activity and a slower royalty stream that depends on a customer's chip succeeding months or years later. A confirmed design start is therefore both current work and a possible future annuity.

At June 2026, annual contract value plus trailing royalties reached $99.5 million, up 44 percent from a year earlier. Remaining performance obligations were $135 million. Enterprise computing averaged 29 percent of that ACV-plus-royalties measure across the previous four quarters, reflecting the pull of data-center and AI work. Automotive remains a natural fit because congestion, deterministic performance and ISO 26262 safety support all matter when a chip is helping watch the road.

Neutrality is the distribution strategy

A customer can build its own bus, crossbar or NoC. It can buy adjacent interconnect technology from a larger IP supplier such as Arm or Synopsys. It can stitch together internal scripts and EDA tools. Arteris's difference is the combination: physically aware NoC generation, coherent and non-coherent fabrics, a record across many silicon designs, integration automation, functional-safety options and now security assurance.

The company calls itself the “Switzerland of IP.” The line works because neutrality has operational meaning. Arteris supports Arm, RISC-V and x86; works alongside Cadence, Synopsys and Siemens EDA flows; and fits projects headed to major foundries. It does not need one processor architecture or one fabrication partner to win. In a market assembled from many vendors' blocks, diplomatic compatibility is a feature.

This would not work everywhere. A small microcontroller with a handful of blocks and modest traffic may be perfectly served by a simple bus. A giant chip company may have mature internal interconnect technology and prefer complete control. NoC configuration also adds its own tools, verification and learning curve. The commercial case gets stronger as the system accumulates cores, chiplets, protocols, power domains, safety obligations and an unforgiving launch date.

More roads, more rules

AI made the old Arteris thesis easier to see. Accelerators multiplied, memory bandwidth became precious, and chiplets turned one piece of silicon into a coordinated system of pieces. Customers now need several networks inside a design, plus software that keeps the inventory connected and evidence that sensitive data cannot take an unintended exit.

Arteris entered the second half of 2026 with fresh deployments at Speedata, SiEngine and Renesas; expanded security work with Arm; and a collaboration with IC-Link by imec for AI and high-performance-computing silicon. The company guided to $95 million to $98 million of full-year revenue. It also remained loss-making under standard accounting. The story is not a tidy victory lap. It is a long engineering bet whose market keeps becoming more complicated in exactly the way the company predicted.

The reader's takeaway is pleasantly unglamorous. Useful infrastructure does not have to own the customer-facing product. It has to remove a recurring failure point, fit the existing ecosystem and accumulate proof that the risky thing has worked before. Arteris found that point between the blocks. Then it followed the work outward - into assembly, software interfaces and security - without leaving the chip.