The Five-Minute Check That Changed the Chip Schedule

At Esperanto, the difference between an hour and five minutes changed the calendar. The chip company was building an AI inference processor around RISC-V cores. Its engineers wanted to check their RTL - the code that describes a chip’s circuits - whenever someone checked in a change. Their earlier lint tool took roughly an hour. Real Intent’s Ascent Lint, according to Esperanto engineer Raj Khanna’s published account, took about five minutes. Suddenly the check could accompany the work rather than interrupt it.

That is an unusually practical definition of speed. A tool can win a benchmark and still lose the engineer if it produces a queue of questionable warnings. Real Intent has built a business around that second half of verification: separating the likely bug from the ceremonial paperwork surrounding it.

Five minutes makes a habit

Chip design is full of checks that everyone agrees are wise and nobody wants to wait for. RTL lint can catch suspicious code before synthesis turns it into gates. Clock domain crossing analysis looks for signals moving between clocks that may not agree on timing. Reset domain crossing analysis follows what happens when parts of the design restart independently. Miss a real problem and a finished chip can behave intermittently, an expensive kind of mystery.

At Esperanto, the quicker lint run made a different workflow possible: checks at every code check-in, whether the change touched a block or the full chip. The team found mismatched signals and other errors that might otherwise surface at synthesis or even later in physical design. Meridian CDC exposed missing synchronizers. Meridian RDC, run late, found issues serious enough that Esperanto changed its reset distribution. The published account says that initial reset setup took about a month and reviewing results another week. Early checks saved time; the late one shows what happens when a useful check joins the party after the furniture has been arranged.

“An hour is really not acceptable for check-ins but five minutes is no problem.”Raj Khanna, Esperanto

Those numbers describe one customer’s flow, not a universal price list. They do explain the mechanism. A check that fits into the workday can alter behavior. A check reserved for the end becomes a negotiation with the schedule.

The company behind the warning

Real Intent was founded in 1998 by Prakash Narain and Rajiv Kumar. Narain had worked on chip design and verification at IBM, AMD and Sun; Kumar had worked on HP processors and server systems. The company began with formal verification and says it moved toward static sign-off around 2010. Formal methods remained in its products, but the offer widened: give a chip team a set of checks it can run from early RTL through final design closure.

The portfolio now reads like a map of ways a modern system-on-chip can betray its maker. Ascent Lint reviews RTL rules. Meridian CDC and RDC inspect clock and reset crossings. Meridian DFT checks whether a chip can be tested after manufacture. SafeConnect verifies intended connections and catches glitches at RTL and netlist level. Conquest Sentry examines hardware security paths. Conquest MAI, announced in 2026, looks for integrity problems in functional building blocks. Riven, also introduced in 2026, is an AI agent for product knowledge, violation review and debugging.

These are enterprise EDA products, sold to teams designing chips rather than to consumers buying them. Pricing is not published. In an earlier Ascent Lint release, Real Intent said price depended on configuration; today it routes prospects through demo and sales requests. The company says more than 50 major semiconductor and systems companies use its software worldwide. Public examples range from Google and Western Digital to Samsung, Nvidia and the open-silicon group lowRISC.

The alarm must know the room

A raw checker can be remarkably good at declaring that something looks odd. It may be less good at knowing whether that oddity is intentional. In a large chip, the difference is not philosophical. Each false alarm asks a human to inspect a path, decide whether it matters, and document the decision. Multiply that by thousands of crossings and “comprehensive” begins to sound like a threat.

Real Intent’s answer is context. Its Meridian CDC analyzes multiple clocking modes in one flow and uses the surrounding microarchitecture to recognize structures such as FIFOs, state machines and counters. The company says its 2026 version can produce reports with up to 98% precision and cut review burden by up to 95%. Those are vendor claims, but they name the right bottleneck: engineer attention. Other EDA vendors sell lint, CDC and formal tools too; Real Intent’s pitch is the combination of capacity, consolidated modes, hierarchical analysis and quieter reports.

One result comes from Western Digital’s published case study: its constraint-driven CDC methodology with Meridian CDC reduced total sign-off time by about two-thirds to three-quarters, reaching two weeks against a typical six to eight. Another comes from lowRISC, which adopted Ascent Lint, Meridian CDC and Meridian RDC for OpenTitan. Its lint setup was folded into the project’s development flow, with scripts and rules aligned to its Verilog style guide. In each case, the tool mattered because it could become a repeatable procedure.

What the schedule can teach

For engineering leaders, the useful imitation is not to buy a particular acronym. Put a cheap, trusted check at the point where a design changes. Make its rules explicit. Reuse setup across blocks. Measure the time from warning to decision, not only the time the engine runs. If review takes longer than the design iteration, a fast algorithm has solved the wrong delay.

That method still needs care. Esperanto’s reset experience shows that some checks require real setup and domain knowledge. Static analysis cannot stand in for every simulation, lab test or engineering judgment. A quiet report is valuable only if its silence is earned. Real Intent’s work sits alongside those methods, at the part of the schedule where discovering a defect is still a modest inconvenience instead of a silicon postmortem.

The company’s newest products push the same idea outward. Conquest MAI tries to infer what familiar circuits are meant to do; Riven tries to speed the human work after a violation appears. Whether those claims hold across every design is a matter for customer projects to establish. The older Esperanto story already proves a narrower point, and a more useful one: when a check takes five minutes, it can become part of making the chip. When it takes an hour, it becomes an appointment.