A semiconductor bug has a peculiar sense of humor. It can announce itself in a simulation log, then hide the reason in a waveform containing millions of signal changes. Somewhere between a specification, a line of RTL and a testbench sits the actual mistake. Finding it can take days. Shipping it can cost rather more.
ChipAgents was built for that search. Founded in 2024 by AI researcher William Wang, the company supplies software agents for chip design and verification. They read specifications, generate RTL and verification assets, run through engineering workflows, and investigate failures across code, logs and waveforms. The ambition is broad: agents that execute meaningful stretches of semiconductor engineering. The evidence is most persuasive when the assignment is narrow enough to measure.
- ChipAgents’ clearest public examples involve verification and debugging, where the output can be checked against tools and tests.
- At eMemory, a documented workflow cut two verification stages from an estimated four days to five hours.
- The company reported more than 120 semiconductor-company deployments and an expanded $134 million Series A in July 2026.
The datasheet becomes a testbench
Consider eMemory, a Taiwan-based supplier of nonvolatile memory intellectual property. Its NeoFuse products arrive with datasheets full of tables, timing diagrams and parameters. Engineers must translate those documents into a verification plan and a Universal Verification Methodology testbench. It is essential work, and also exactly the sort of work a team can spend a week repeating.
In a September 2026 customer announcement, eMemory said ChipAgents processed ten NeoFuse datasheets, checked their contents against an internal specification database, and generated a verification plan and UVM testbench. The company reported zero extraction mismatches across those documents, detected all 15 deliberately planted datasheet errors with no false positives in that test, and found five issues when it later ran a quality check across 100 manually edited production datasheets. Those are bounded evaluations, not a universal accuracy guarantee. They are useful precisely because one can see the task.
The measured reduction in those two stages was about 80%. Functional coverage rose by five percent. eMemory’s CAD director Max Yeh said the tool also helped improve the “quality and reliability” of its IP datasheets. That last detail is telling: the agent did more than type faster. It made documentation defects visible before they could be translated into tests.
The first answer is usually the dangerous one
This is why a generic coding assistant is an awkward fit. It may produce convincing Verilog. Convincing is not a verification result. In chip development, the design must survive simulation, satisfy constraints and preserve behavior across situations that no single prompt can describe. A plausible explanation for a failure can waste an engineer’s afternoon; a plausible fix can create another failure.
ChipAgents’ root-cause product, RCA, begins with a different premise: the evidence lives in several places. Its published technical description says the system indexes compressed waveform data so an agent can ask focused questions about signal changes instead of trying to absorb an enormous trace. It then runs a prover-verifier loop, where one agent proposes a cause and another checks it. Candidate explanations are ranked for the engineer. This is the useful distinction from a chat window: the proposed answer has to return to the evidence.
A Whalechip deployment shows what that can mean in practice. During a 60-hour debugging effort on a new chip, the company said ChipAgents found four critical bugs in a customer memory controller, including a hidden three-cycle race condition. Its reported root-cause rounds fell from days to 15 to 60 minutes. The release does not turn every debug session into a fifteen-minute job. It does show where the software earns its keep: narrowing a large search space while the engineer still owns the decision.
“We’re enabling the industry to move beyond AI assistants toward autonomous agents that can execute meaningful engineering work.”William Wang, founder and CEO
A laboratory meets the EDA floor
Wang’s route into this market was unusual. He had spent years on language models and machine reasoning, including research at Carnegie Mellon and a professorship at UC Santa Barbara. ChipAgents says it began in that university AI lab with a professor and a few students. The team’s original question was whether advances in reasoning could be made useful in chip design, a field where the most valuable data is often locked inside companies and the answer is judged by unforgiving tools.
By 2025, the company had settled on verification as a practical wedge. It published work on autonomous root-cause analysis and raised a $21 million Series A. In 2026 came another $50 million, then a further $60 million. The expanded Series A reached $134 million, with B Capital joining investors that included Bessemer Venture Partners and strategic backers Micron and MediaTek. ChipAgents also reported sixfold annual recurring revenue growth in the first half of 2026. Neither revenue dollars nor valuation were disclosed in that announcement.
The customer list gives the funding story more shape. MediaTek and Micron are named deployments. Ambiq expanded its use after an evaluation. Andes Technology reported using the platform on several processor design and verification projects; one processor customization task shrank from 8.5 weeks to six. These numbers belong to different jobs, customers and baselines. They should be read as case studies, not a single promise that every chip project will run on the same clock.
The model has to fit behind the wall
ChipAgents’ market sits beside the established electronic design automation stack. Synopsys and Cadence supply many of the tools chip teams already use, and both have AI work of their own. ChipAgents’ pitch is an agent layer that can move across specifications, RTL, verification plans, simulators and debug evidence. Its software is sold to enterprise teams through demonstrations and negotiated deployments; no public list price is posted.
The company’s Renoir model addresses another buying condition: many chip companies cannot send proprietary designs and logs to a public AI service. Introduced in June 2026, Renoir is designed for customer-controlled, including on-premises, deployment. ChipAgents says it fine-tuned an open-weight model on curated semiconductor tasks and built it to work with its agent system. It later expanded a collaboration with NVIDIA to help train and optimize that system. The published performance comparisons use ChipAgents’ internal benchmarks, so buyers should test on their own designs.
What can another engineering team copy? Begin with one expensive, repetitive task whose output has an independent check. Record the manual baseline. Give an agent the specification and the right tool access. Then compare generated plans, code and diagnoses against simulator results and expert review. This is the pattern behind eMemory’s datasheet workflow and Whalechip’s debugging effort. It is less theatrical than asking an AI to design a chip. It is also easier to know when it worked.
There are limits. If the specification is ambiguous, the simulation environment is unreliable, or the design cannot be safely made available to the agent, automation has little stable ground to stand on. Physical implementation and timing closure may also have slower feedback loops than frontend verification; ChipAgents itself describes that as a harder next step. The company’s proposition depends on fast, trustworthy validation, disciplined data controls and engineers willing to inspect the result.
That is the appealing irony of ChipAgents. It sells a future in which agents do more engineering, yet its best stories are about making the engineer’s judgment sharper. The work begins with a datasheet. It ends, if all goes well, with one fewer mystery inside the silicon.