BREAKING 2025: Breker RISC-V SystemVIP deployed across 15+ commercial chip projects OCT 2025: Breker donates advanced test suite to RISC-V International for compliance Founding member of the Accellera Portable Stimulus Standard 5X faster test composition - 4X coverage SINCE 2003: Test Suite Synthesis, invented in Silicon Valley 62nd Design Automation Conference - exhibitor BREAKING 2025: Breker RISC-V SystemVIP deployed across 15+ commercial chip projects OCT 2025: Breker donates advanced test suite to RISC-V International for compliance Founding member of the Accellera Portable Stimulus Standard 5X faster test composition - 4X coverage SINCE 2003: Test Suite Synthesis, invented in Silicon Valley 62nd Design Automation Conference - exhibitor
Company Profile · Electronic Design Automation · San Jose, CA

Breker Verification Systems

The Silicon Valley company that decided chip engineers were spending too much of their lives writing tests by hand - so it taught software to write them instead.

Founded 2003 Test Suite Synthesis RISC-V Verification ~19 People
Pictured: a logo that has sat quietly inside the verification flow of chips you have almost certainly used. No, they will not tell us which ones.
Who they are now

A 19-person company sitting in the critical path of modern silicon

Somewhere right now, a verification team is staring at a chip with billions of transistors and a deadline that arrived yesterday. The design has to work the first time. Re-spinning a modern system-on-chip costs millions and months. And the test cases that prove it works are, traditionally, written by humans, one painstaking scenario at a time.

Breker Verification Systems exists in that exact moment of pressure. The company builds software that reads what a chip is supposed to do and then generates the multi-threaded, self-checking test cases that hammer on it - automatically, in parallel, across simulation, emulation and actual silicon. It is not a household name. It employs around nineteen people out of San Jose. And it has spent more than two decades sitting in a spot that very few people understand and almost no chip ships without.

Breker is the pioneer of Test Suite Synthesis and System Verification IP. Breker Verification Systems
The problem they saw

Verification was eating chip design alive

Here is the inconvenient truth of the semiconductor industry: designing the chip is the easy part. Proving it works is where projects go to die. By some industry estimates, functional verification consumes the majority of an SoC project's engineering effort. Every new feature multiplies the number of ways the thing can fail. Every processor core you add multiplies the interactions you have to test.

The standard answer, for years, was to throw people at it. Write more testbenches. Hand-code more UVM sequences. Hire more verification engineers than design engineers. It worked, in the way that bailing water out of a boat works - right up until the chips got too complex and the water came in faster than anyone could scoop.

Designing the chip is the easy part. Proving it works is where the schedule goes to die. The verification engineer's lament

Adnan Hamid had seen this from the inside. Before Breker, he managed AMD's System Logic Division and led the team that built the first test-case generator delivering 100% coverage for an x86-class microprocessor. He had also spent years at Cadence as a system-level verification expert, building solutions for the likes of Texas Instruments, Motorola and General Motors. He knew the bailing-water problem was structural. The fix could not be more people. The fix had to be a machine.

The founders' bet

Generate the tests. Don't write them.

In 2003, Adnan Hamid and Maheen Hamid - co-founders, and as it happens, married - made a bet that sounds obvious now and sounded heretical then: that verification intent could be captured once, as a model of what a chip is meant to do, and that test cases could be synthesized from that model the way a logic synthesizer turns RTL into gates. Adnan invented the core technology. Maheen, as COO, ran the operations, finance and the unglamorous machinery that keeps a venture-backed company alive.

Founder · Exec President & CTO

Adnan Hamid

Inventor of Breker's core technology. Ex-AMD verification lead and ex-Cadence system-level expert. BS in EE and CS from Princeton; MBA from UT Austin's McCombs School. Named a Top Embedded Innovator by Embedded Computing Design.

Co-Founder & COO

Maheen Hamid

Runs operations, finance, and sales and marketing. The half of the founding pair that turned a deep technical idea into a company that has outlasted most of its better-funded contemporaries.

The fix could not be more people. The fix had to be a machine. The Breker thesis, paraphrased

They raised a grand total of about $5 million - a rounding error by EDA standards, where the incumbents spend that on a sales kickoff. The last round, a Series A, closed in 2012. What Breker did with that modest sum is the genuinely interesting part.

The product

What the machine actually does

Breker's tools take a description of intended behavior and explore every meaningful path through it - then emit test cases that are multi-threaded, run across multiple processors, and check their own results. The same intent gets reused from block-level simulation all the way to post-silicon bring-up. You write the scenario once. The tool finds the corner cases you would never have thought to type out at 2am.

Trek Suite

TrekUVM, TrekSoC and TrekSoC-Si - the synthesis engines that auto-generate self-verifying tests for block, SoC and post-silicon environments.

SystemVIP

Verification IP libraries for cache and system coherency, RISC-V and Arm SoCReady, Security Hardware Root of Trust, and power management.

RISC-V CoreAssurance

Synthesized verification IP aimed at certification-level coverage for RISC-V cores and SoCs in data center, automotive, AI and consumer chips.

Portable Stimulus

Author intent in the Accellera PSS standard or native C++, then reuse it across simulation, emulation and silicon. One model, many platforms.

You write the scenario once. The tool finds the corner cases you would never have typed out at 2am. Caption to a problem every verification engineer recognizes
Milestones

Two decades, told in dots

2003

Breker is founded

Adnan and Maheen Hamid launch the company in Silicon Valley around the idea of synthesizing verification test content.

2012

Series A closes

The company's last disclosed funding round - roughly $5M total raised across its life.

2015 onward

Portable Stimulus, the standard

Breker becomes a founding member of the Accellera Portable Stimulus Working Group and donates substantial technology to the effort.

2021

A new chapter at the top

David Kelf is named CEO; founder Adnan Hamid moves to Executive President and CTO to focus on technology and growth.

2025

RISC-V everywhere

RISC-V SystemVIP deployed across 15+ commercial projects; Breker donates advanced test suite components to RISC-V International.

2026

Toward agentic verification

The company starts asking aloud whether AI agents can build verification models - the next bet, taking shape.

The proof

The numbers do the arguing

Skepticism is the correct posture toward any vendor claiming to save you time. So here is what Breker reports, and where it comes from. At major semiconductor firms, the company cites a 5X reduction in test composition time and a 4X increase in coverage versus hand-written effort. Its RISC-V SystemVIP is deployed across more than 15 commercial chip projects, and it has engaged with more than 20 RISC-V core producers. Treat the multipliers as the vendor's own figures - but the deployment count is harder to wave away.

Manual testbenches vs. Breker synthesis

Relative, per Breker's reported results at major semiconductor firms. Higher coverage bar = better; lower time bar = better.
Coverage - manual
1X
Coverage - Breker
4X
Compose time - manual
5X (slow)
Compose time - Breker
1X
2003
Founded
15+
RISC-V projects
20+
Core producers
5X
Faster composition
Build chips 10X faster and at 50% lower cost - without changing your flow. Breker's own pitch, on the record

The partnerships tell their own story. Breker is a founding member of the Accellera Portable Stimulus Working Group, contributing the technology that became an industry standard. In 2025 it donated a subset of its RISC-V test suite to RISC-V International for future compliance and certification work, with Breker executives chairing related working groups. It has also partnered with Agnisys to generate system-level portable stimulus sequences. Known users include Broadcom and Condor Computing - the latter's president publicly crediting Breker with real advantages over standard verification.

The mission

A standard is just a bet that other people will follow

Breker's stated mission is unfussy: "to drive the evolution of verification technology with a single-minded focus on our customers' success." What is striking is how a company this small has shaped tooling this large. Donating core technology to Accellera and RISC-V International is not charity - it is the long game. If the whole industry standardizes on the way you think about verification, you do not need to be the biggest vendor. You need to be the one who got there first and stayed.

If the whole industry adopts the way you think, you don't need to be the biggest. You need to have been first. On why a 19-person company gives its technology away
Why it matters tomorrow

The next bet has a name: agentic verification

RISC-V is no longer a research curiosity - it is heading into data centers, cars and AI accelerators, all of which need verification that can stand up to certification. That is squarely Breker's terrain. And the company is already circling the next problem: it has begun publicly asking whether AI can create the missing verification models, and what "agentic verification" - AI agents that test silicon - would actually take. It is the same instinct that started the company in 2003. See the place where humans are doing too much by hand. Build the machine.

Back to that verification team, staring at billions of transistors and a deadline that arrived yesterday. Two decades ago they would have started typing test cases and prayed they thought of everything. Today, increasingly, they describe what the chip should do and let Breker's tools go hunting for the failures - across cores, across coherency, across silicon. The deadline is still yesterday. The boat is still taking on water. But for the first time, something other than a human hand is doing the bailing - and it does not get tired at 2am.

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Profile compiled from public sources. Figures such as "5X" and "4X" are company-reported; funding and headcount are approximate per public records.