The engineer who taught machines to test the machines
Ask most people how a computer chip gets checked before it ships, and you will get a blank look. Ask Dave Kelf, and you will get a career. As chief executive of Breker Verification Systems, Kelf runs a San Jose company that most consumers will never hear of, yet whose software now touches a striking share of the silicon being designed today.
Breker builds what the industry calls test suite synthesis - tools that automatically generate the enormous batteries of tests needed to prove a complex chip works before a single unit is manufactured. Under Kelf, those tools have become a fixture of the RISC-V movement, the open processor architecture reshaping the semiconductor world. By the company's own account, Breker is now used on more than half of all RISC-V processor core developments globally.
That reach did not arrive overnight, and neither did Kelf. He has spent three decades in electronic design automation, or EDA, the small but essential corner of tech that makes the software chip designers rely on. Along the way he kept turning up at the exact companies where the next big idea in verification was being born.
A career measured in languages and tools
Kelf trained as an engineer in the United Kingdom, earning a bachelor's degree in electronic computer systems from the University of Salford and a master's in microelectronics from Brunel University. An MBA from Boston University followed, giving him the rare double footing of technical depth and business fluency that would define his path.
At Cadence Design Systems, he ran sales and marketing for both the Verilog and VHDL verification product lines - the two rival hardware description languages engineers argued over for years. Later, as vice president of marketing at Co-Design Automation, he oversaw the introduction and growth of SystemVerilog, a language now used on virtually every large chip design on the planet. He ran marketing for Novas Software, known for its industry-leading Verdi debug environment, a company that became Springsoft and is now part of Synopsys. He was president and CEO of Sigmatix, and later vice president of worldwide marketing at formal verification specialist OneSpin Solutions, now part of Siemens EDA. For a stretch he served as treasurer of Accellera, the standards body that governs much of how the industry agrees to work.
The pattern is hard to miss. Kelf has a habit of landing where verification gets reinvented - SystemVerilog at Co-Design, Verdi at Novas, and now RISC-V verification at Breker. It reads less like luck than like a nose for the next hard problem.
From marketer to chief executive
Kelf joined Breker as chief marketing officer, also managing the company's sales channel. In October 2021, Breker named him CEO, with founder Adnan Hamid moving to executive president and chief technology officer. A marketer stepping into the top job is unusual in an industry run largely by engineers, but Kelf's technical training meant he could speak the language of the customers he had spent years explaining the technology to.
The results since have been steady rather than showy. Breker recorded 35 percent revenue growth from 2023 to 2024, then matched it again from 2024 to 2025. The company doubled its customer base, added several top-10 semiconductor firms and two members of the so-called Magnificent 7, and opened an engineering and support facility in Bangladesh to keep up with demand.
The case against the homebrew test bench
Kelf's core argument is a practical one. Verification engineers, he says, spend far too much of their time and resources building one-off, homemade test setups for system-level scenarios - work that is tedious, error-prone, and rarely reusable. His answer is synthesis: let the software generate the tests, and let planning algorithms hunt for the corner cases a tired human would never think to check.
That thesis has pushed Breker toward artificial intelligence. The company partnered with Moores Lab AI to build what it describes as the first AI-driven SoC verification flow, pairing its Trek test suite synthesis with agentic AI. Kelf frames automated test content generation as the single biggest growth opportunity in verification for the years ahead.
He remains, by reputation, an accessible and collaborative figure - the kind of executive who lists the website, LinkedIn, and X as the ways to reach him and means it. In 2025 he took the stage at DAC, the industry's marquee conference, on a panel titled "What is the Future of Design Verification? UVM, PSS, Formal, VIP, AI & Beyond," and at an Accellera luncheon focused on portable stimulus. Both are exactly the standards-and-language debates he has been part of his whole career.
For all the growth charts, Kelf's ambition is narrow and specific: he wants test suite synthesis to become a default part of every complex chip project, the way SystemVerilog became a default language. If he is right that verification is nearing an inflexion point, the company he runs has positioned itself, quietly, to be standing on the other side of it.