Visibl Semiconductors is teaching AI to catch the quiet mistake that costs chip teams $20 million

Somewhere in a chip design, a line in a specification changes. Maybe a clock domain moves, maybe an interface widens by a bit. The engineer who made the change updates the spec, mentions it in a Slack thread, and moves on. Three weeks later, the verification team is still testing against the old behavior, because nobody told the test bench. The gap sits there, invisible, until it surfaces in silicon - at which point fixing it means a respin that can run $5 million to $20 million and push the schedule out by the better part of a year.

That gap has a name inside the industry: drift. It is the slow divergence between what a chip was supposed to do, what the design says it does, and what the hardware actually does. And it is the single problem that Visibl Semiconductors, a two-person startup in Y Combinator's Winter 2026 batch, has decided to build an entire company around.

The pitch is unusually narrow for an AI company, which is part of why it is interesting. Visibl is not trying to design your chip for you. It is trying to notice the moment your chip design stops agreeing with itself.

The problem

Chips don't usually fail on physics

Ask an outsider why a chip program slips and they will guess something exotic - a transistor that won't switch fast enough, a thermal wall, some frontier of quantum weirdness. Ask the people who actually ship silicon and you get a duller answer. Programs fail on coordination.

A modern chip is described in a sprawl of artifacts: a written specification, tens of thousands of lines of RTL code in SystemVerilog or Verilog, synthesis scripts, verification suites, CI pipeline results, and the outputs of proprietary tools from Synopsys, Cadence and Siemens. Those artifacts are supposed to describe one coherent design. In practice they live in different files, different tools, and different people's heads, and they fall out of sync constantly.

The current fix is human attention: senior engineers who hold the whole design in their memory and catch discrepancies in review. That works until the team grows, the design gets big, and the tapeout deadline compresses. The very moment coordination matters most - integration, design freeze, pre-tapeout - is the moment there is least slack to do it by hand.

// Figures per Visibl's public materials; respin costs are industry estimates.

The product

A loop, not a copilot

Visibl describes its core product as a coordination layer, and it runs as a four-step loop. The design matters less as branding than as a statement of what the company will and won't let its AI do.

That last step is the tell. In a year when much of the AI industry is racing to build agents that act on their own, Visibl's headline design choice is restraint. No change to a chip - where an error is measured in millions and months - reaches silicon on the AI's say-so. The machine finds the problem, documents it, drafts the fix, and then stops and asks.

There is a second product visible in the company's public footprint: an AI-powered EDA IDE it calls Orchestrator, with AI-driven architecture tools, an intelligent HDL editor and collaborative features, offered as a free download for Windows, macOS and Linux. It reads as a wedge - a way into risk-averse hardware teams that lets engineers try the technology before trusting it with the coordination layer proper.

The founders

Two people who have shipped real silicon

Deep-tech tooling lives or dies on whether the founders have actually done the work. Visibl's have. Jordon Kashanchi, the CTO, has worked on silicon at Microsoft, Arm and Intel - AI accelerators, autonomous-vehicle hardware, and graphics chips. Most recently at Microsoft he designed digital logic and microarchitecture for next-generation custom AI silicon. He holds an MS in ECE from UT Austin and, in an unexpected footnote, is published in PNAS and ACM for research on wearable biosensors.

Bryce Neil, the CEO, comes from the software side - a computer engineer who built production software and data systems for Deloitte's Omnia AI, plus healthcare and public-sector projects, and who picked up two of Canada's most competitive academic scholarships along the way. The split is the point: one founder who has felt the pain of a chip program from the inside, one who has built the kind of always-on data plumbing this product needs.

The market

Winning the space between the giants

The obvious question for any chip-tooling startup is: what happens when Synopsys or Cadence does this? The two incumbents together carry something like $160 billion in market value and own the tools engineers already use. The EDA market itself is projected to reach roughly $23.9 billion by 2030.

Visibl's answer is positional. The incumbents are adding AI inside their own tools - a smarter simulator, a better place-and-route. Visibl is going after the coordination problem between tools, which no single vendor owns because no single vendor sees the whole picture. It is a classic wedge: pick the seam the big players structurally can't close.

// Bars are a qualitative sketch of positioning, not measured market share.

There is a labor angle too. The industry is projected to be short roughly 23,000 semiconductor engineers by 2030. If Visibl can genuinely cut the time engineers spend hunting down misalignments - it claims something near a 90% reduction in troubleshooting overhead - the value is not only fewer respins but more output from the engineers who exist.

The moat question

Why this is hard to copy

The technical difficulty is also the defensibility. Reading a chip design is not like reading a web app. The data is heterogeneous and proprietary: SystemVerilog and Verilog, synthesis scripts, and the outputs of tools like Synopsys VCS, Cadence Xcelium and Siemens Questa. Visibl argues this demands multi-modal understanding of deeply technical engineering artifacts, handled by fine-tuned models rather than off-the-shelf LLMs.

Then there is trust. Chip IP is among the most closely guarded material in technology, which is why Visibl deploys on-premises - the AI comes to the data, and the design never leaves the building. For a customer weighing whether to let a startup near its crown jewels, that architectural choice may matter as much as the model quality.

The bet

Will it matter?

Visibl is early - founded in 2024, a $130,000 YC seed, a team you can count on one hand. The claims about cost and time savings are the company's own, and the customer base is measured in early design teams rather than logos. What it has is a clear thesis, founders who have lived the problem, and a wedge the incumbents are structurally poorly placed to defend.

The larger idea travels beyond chips. In any complex project, information rarely gets lost so much as scattered, and the expensive failures happen in the gaps between systems that each think they hold the truth. Visibl's wager is that the valuable AI is not the one that produces more - it's the one that notices when two sources of truth have quietly stopped agreeing, and knows to ask a human before it acts. In semiconductors, being wrong about that costs $20 million. It is a good place to test whether the bet holds.

// Video: Visibl has not published a product demo or founder interview at time of writing. Check the YC and LinkedIn pages above for updates.