S2C Builds the Chip Before the Chip

There is a strange interval in the life of a new chip. The design exists, but the chip does not. Millions or billions of logical gates have been described in code. Architects argue about caches. Firmware engineers wait. Drivers wait. The final silicon, once ordered, will be expensive and stubbornly physical. It cannot be fixed with a keystroke. In this interval, S2C builds a convincing impostor.

The impostor is made from field-programmable gate arrays, or FPGAs: reconfigurable chips wired and programmed to behave like the future ASIC or system-on-chip. Put enough of them together, add the right interfaces, and an engineering team can boot an operating system, attach storage, exercise a camera, push packets, and discover which assumptions collapse under contact with the real world. S2C's business is to make that process less like a laboratory stunt and more like repeatable infrastructure.

The clever product is not the FPGA box. It is time - specifically, the time between “the logic compiles” and “the silicon arrives.”

Four people bet against the waiting room

Toshio Nakama encountered FPGAs in a digital-circuit course at Cornell, then worked at Altera and at Aptix, a pioneer in programmable interconnects. In 2003, he, two other former Aptix principals, and a finance professional pooled their money to start S2C in Silicon Valley. Their timing was unfashionable. Software simulation and hardware emulation occupied the center of verification. FPGA prototypes were powerful but largely reserved for big design houses able to assemble custom systems and tolerate difficult tools.

The founders saw two openings. The first was technical: package the hardware with the tools and reusable interfaces ASIC designers actually needed. The second was geographic. A new class of Asian semiconductor companies and design centers was emerging. S2C established engineering and manufacturing in Shanghai in 2004, close to both talent and customers who might try a young methodology. That proximity mattered. Early FPGA prototyping needed what Nakama called a fair amount of handholding.

The first failure, in other words, was not usually the logic. It was the workflow around the logic. A design too large for one FPGA had to be divided without ruining timing. Signals had to cross chip boundaries. Physical interfaces had to be recreated. Debug visibility had to survive the partition. S2C's answer was a system: hardware, compilation, partitioning, run control, debug, transaction links, and ready-made peripheral cards.

A rehearsal room with 90 kinds of door

Prodigy is the umbrella name. Logic Modules handle compact jobs. Logic Systems package one, two, or four large FPGAs in configurable enclosures. Logic Matrix scales outward in server racks for designs measured in billions of equivalent ASIC gates. The current S8-100 uses AMD's Versal Premium VP1902 and offers 100 million equivalent ASIC gates per FPGA. S2C says it doubles the logic resources and delivers 2.5 times the I/O bandwidth of its S7-19P predecessor.

The hardware would be a rather expensive paperweight without the rest. Player Pro compiles, partitions, configures, monitors, and controls the prototype. Multi-Debug Module Pro traces signals across several FPGAs. ProtoBridge moves transaction-level data between a host model and the device under test. Neuro lets organizations manage prototype resources across teams and locations. Then there is the wonderfully unglamorous Prototype Ready IP catalog: more than 90 daughter cards, adapters, memory models, and interfaces.

Those little boards explain S2C better than a giant gate count does. A prototype becomes useful when it can meet the world: PCIe, Ethernet, DDR memory, MIPI cameras, storage, displays, and debug ports. Every pre-validated interface removes another bespoke integration job. The company is not merely selling programmable logic. It is selling fewer reasons for the prototype to remain on the bench.

The software team stops being the last guest

StarFive offers the neatest public example. While developing its Jinghong 7100 RISC-V platform, the company needed to validate deep learning, image processing, speech recognition, and machine vision before the final device existed. A Prodigy Virtex UltraScale system let its hardware and software work begin together. StarFive vice president Hu Jian said the team started integration before the RTL was complete and cut two months from the development schedule.

That is the change of mind S2C keeps trying to provoke. Prototyping is not a final hardware check. It is a shared workspace. Drivers can be written against something responsive. Operating systems can boot. Interfaces can misbehave in informative ways. Customers can sometimes receive an evaluation platform before they receive the chip. Artosyn, which develops AI processors for drones and vision systems, has described building customer prototypes on S2C hardware so those customers could start software earlier.

The newer RISC-V work makes the same point at a larger scale. S2C and Andes have run processor IP, Linux virtualization, and AI inference on the S8-100. With MachineWare, the pair connected virtual CPU models to physical FPGA peripherals, preserving detailed software-model visibility where it helps and hardware speed where it matters. In 2026, Andes named S2C its Partner of the Year.

Nobody publishes the price of avoiding a late bug

S2C does not list standard prices. A system depends on FPGA count, interfaces, software, service, and support, so the sale is consultative and quote-based. That makes the buying equation less tidy than ordering a development board. The other side of the equation is also untidy: engineering months, a delayed tapeout, or software that begins only after silicon arrives.

The company itself raised a disclosed $4.6 million Series C in 2014 from GVT Fund and Industrial Technology Investment Corp. The money was earmarked for sales, support, research, and a then-forward-looking idea: turn prototyping into a remotely available enterprise resource. S2C was acquired by SMiT Group in 2018. Revenue and valuation are not public.

Its market sits between do-it-yourself FPGA boards and the broad verification suites of Synopsys, Cadence, and Siemens. A home-built platform can be sensible for a small, stable design and an expert team. S2C becomes more interesting as the system grows, the software becomes central, the interfaces multiply, and the cost of maintaining custom infrastructure begins to swallow the apparent savings.

The honest limits of the rehearsal

An FPGA is not the final silicon. Clock behavior differs. Some analog effects cannot be reproduced. A vast design may need to be split across devices, and every crossing complicates timing and debug. The approach is a poor bargain when the design already fits a cheap board, when the problem is best settled by formal proof or block-level simulation, or when a team lacks the specialists to operate a prototype.

But for software-heavy systems with real peripherals and a costly manufacturing commitment ahead, the imitation can be more useful than its imperfections suggest. It lets the organization discover ordinary, consequential things: the driver assumes the wrong reset sequence; the interconnect stalls under load; the camera is not quite the camera in the model. The first failure becomes something the team can see early, while changing its mind is still affordable.

That is S2C's durable proposition. The company began by making FPGA prototyping accessible to teams that could not afford to invent the method themselves. Two decades later, the designs are larger, the boxes are denser, and the software stacks are heavier. The interval before silicon remains. S2C has simply made it a place where more work can happen.