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Primemas Wants to Make the Most Expensive Part of a Chip Boring
Its Hublet architecture separates the clever part of a custom chip from the expensive plumbing around it. The bet is that AI builders would rather buy that plumbing once than reinvent it for every product.
The Chip That Tried to Borrow Time
Tabula spent twelve years teaching a flat chip to impersonate a stack of chips. The trick worked well enough to win Cisco, Intel, and more than $200 million - but not well enough to escape the oldest trap in programmable logic.
The 37-Year-Old Telecom Engineer Teaching AI to Watch Every Packet
Telesoft spent decades learning how carrier networks behave. Now it is turning that hard-won packet craft into an on-premise security stack for organisations that cannot afford blind spots - or send their most sensitive traffic to somebody else’s cloud.
Intel
The company that built the microprocessor is trying to build something harder: a second act. Inside Intel's bet-the-house pivot from selling chips to making everyone else's.
Visibl Semiconductors
Visibl Semiconductors (YC W26) is a San Francisco startup building an AI-native coordination layer for chip design. Its software watches specifications, RTL code, CI pipelines and EDA tool outputs for 'drift' - the slow divergence between what a chip was supposed to do and what the design actually does - then opens evidence-backed cases and proposes review-ready fixes that a human must approve before anything ships. Founded by Bryce Neil (CEO) and Jordon Kashanchi (CTO), the company targets verification and methodology owners on teams heading toward integration, design freeze and tapeout, where a single missed misalignment can trigger a $5M-$20M respin.
Zero-Error Systems (ZES) Pte Ltd
Zero-Error Systems (ZES) is a Singapore deeptech semiconductor company and Nanyang Technological University spin-off that builds radiation-hardened integrated circuits, radiation-tolerant system-on-modules, and irradiation testing services. Its patented radiation-hardened-by-design technology protects low-cost commercial-off-the-shelf (COTS) electronics from radiation effects such as single-event latchup, letting satellite and space-system makers achieve space-grade power reliability and data integrity at a fraction of traditional rad-hard cost.
DualBird
DualBird is a Boston-based data infrastructure company building a cloud-native engine that brings hardware-grade acceleration to big data and AI workloads. By running rewritable FPGA silicon on AWS as a software service, DualBird plugs into existing Apache Spark and Apache Iceberg pipelines and claims 10-100x faster processing at 50-90% lower cost, without asking teams to change their code or workflows. The company raised $25M in combined Seed and Series A funding led by Lightspeed Venture Partners in November 2025.
Grovf
Grovf is a deep-tech semiconductor startup building AI infrastructure backend networking - RDMA and chiplet IP, soft IP cores, and scale-out NICs that connect AI accelerator servers at 400/800Gbps with sub-2-microsecond latency. Founded in 2017 in Armenia by Artavazd Khachatryan and Khachik Sahakyan, the company began with FPGA-accelerated databases for the Industrial IoT and evolved into networking fabric for large-scale AI model training. Grovf was the first company from Armenia and the Caucasus to win an EU Horizon 2020 SME Instrument grant, and went through UC Berkeley's SkyDeck accelerator.
Artis
Artis, LLC (Advanced Real-Time Information Systems) is a Herndon, Virginia defense and technology developer that builds systems for problems measured in microseconds. Founded in 1999 by Keith Brendley, the company is best known for active protection systems for military vehicles - Iron Curtain and its third-generation successor, Sentinel - that detect and defeat incoming rockets, missiles and drone-borne threats in fractions of a second. Beyond defense, Artis applies its high-speed sensing and parallel-processing work to highway worker safety, 3D imaging and pedestrian monitoring.
Positron AI
Positron AI designs purpose-built inference hardware for transformer models, aiming to make Nvidia GPUs optional for running large language models at production scale. Its first product, Atlas, ships from US fabs and claims roughly 3x lower latency and 4x better performance-per-watt versus an H100 system.