Here is a fact about modern computers that almost nobody outside the industry thinks about: the hard part is often not the chip, but the wires between chips. A data-center accelerator is only as fast as the links carrying bits into and out of it, and those links - the serializer/deserializer circuits known as SerDes - are fiendish analog problems dressed up in digital clothing. eTopus Technology, founded in 2012 in San Jose, does essentially one thing, which is design those links and license the design to whoever is building the chip.
This is a good business to be in, in the specific and slightly boring way that plumbing is a good business. Everyone building a high-performance chip needs interconnect. Almost nobody wants to design it from scratch, because it is the kind of mixed-signal, data-converter, error-correcting-code work that takes a small team of very patient PhDs a very long time to get right. So they license it. eTopus's founders - CEO Harry Chan, CTO Peter Kou, and analog VP Danfeng Xu - have spent two-plus decades each on exactly this problem and hold something like 80 patents between them. The company is, by headcount, tiny: roughly 49 people. By intellectual-property density it is enormous.
The technical bet eTopus made early was on ADC/DSP-based SerDes. Instead of handling the incoming high-speed signal with purely analog equalization, this approach digitizes it with a data converter and then cleans it up in the digital domain with signal processing. In 2016, eTopus was shipping this at 56Gbps with PAM-4 signaling, at a time when much of the industry had not committed to the approach. It turned out to be the right call; ADC/DSP SerDes became the dominant architecture at advanced nodes. Being early in semiconductors is a peculiar kind of bet - you place it years before anyone can tell you were right, and the payoff is that when the market arrives, you already have silicon-proven IP on the shelf.
What is on the shelf now is a portfolio that reads like a bandwidth roadmap: 112G serial on 6nm and 7nm, 56G on 16nm and 12nm, up to 58G on 22nm, plus an ultra-low-latency 400G IP. The pitch reduces to two words that usually fight each other - low latency, low power - and eTopus claims a combined FEC-plus-SerDes latency "well under 10ns," against the roughly 100ns per link it attributes to some competing designs. Latency numbers in marketing material deserve the usual skepticism, but the direction is the point: in AI clusters, where the same data crosses many links, nanoseconds compound.
"An innovator and technology leader in high-performance, DSP-based, mixed-signal, ultra-high-speed semiconductor interconnect solutions."
The more interesting recent move is chiplets. The industry is breaking single large expensive chips into several smaller cheaper ones, which is great for yield and cost and terrible for the wiring, because now all those dies have to talk to each other over standardized die-to-die interfaces like UCIe and Bunch of Wires. This is directly adjacent to what eTopus already does, and the company leaned in. In 2022 it announced a collaborative chiplet IP platform, and with QuickLogic it shipped what the two called the industry's first disaggregated, flexible eFPGA chiplet template - a 6nm starting point, with configurable logic, memory and DSP, that others can build on. With CoMira it added PCIe Gen 1-6 and 800G support for 7/6nm. The strategy is to be the interconnect layer of the chiplet era rather than one more full-chip vendor.
The cap table reflects how quietly geopolitical interconnect IP has become. Early money came from SK Telecom Ventures and cross-border funds; a $13.75M Series B in 2023 was led by Hua Capital, and a follow-on Series B II in 2024 brought in Qingzi Zeyuan Capital. Korean and Chinese strategic investors backing a Silicon Valley SerDes company is not an accident - everyone wants a stake in the roads inside the chip. eTopus competes, at wildly different scale, with Alphawave Semi, Synopsys, Cadence, Rambus and Credo. It is the small, specialized shop in a field of giants, which is either a precarious place to be or exactly the right one, depending on how the chiplet transition plays out.
