Here is a fact about semiconductors that sounds like a riddle: the fastest part of a modern chip is also the part that agrees on time. Billions of transistors, all switching in something close to unison, all taking their cue from a clock. When the clock is a little off - when its edges arrive at slightly different moments in different corners of the die - the whole thing has to slow down to be safe. Engineers pad their timing margins, leave performance on the table, and ship a chip that runs below what the physics allows. Movellus is a company built on the premise that this is a solvable problem, and that solving it is worth a business.
Movellus makes semiconductor IP. Not chips - the intellectual property that goes inside other people's chips. Specifically, it makes the infrastructure blocks: the clock networks that distribute timing, the circuits that detect and respond to voltage droop, the on-die sensors that report a chip's health, and, more recently, the regulators that deliver power on the die itself. It licenses these as synthesizable, digital IP, which is the interesting part, because most of these functions have traditionally been analog - hand-tuned by specialists, redone for every process node, jealously guarded.
The thesis Movellus has been quietly proving for a decade is "synthesizable analog": take the blocks that used to require an analog wizard and a fresh start on every node, and turn them into something a digital design team can drop into a flow and port from 40nm to 3nm without rebuilding from scratch. Portability is the pitch. In an industry where redesigning a clock generator for a new process can consume months, "it moves with you" is a genuine value proposition.
The company's product family is called Aeonic, and it has grown in a logical arc. First came Aeonic Generate, the clock generation module - the original Intelligent Clock Network idea, using what Movellus calls Smart Clock Modules to trade transistors for lower timing skew and better margins. Then came the war on droop.
Voltage droop is one of those problems that is invisible until you know to look for it, at which point it is everywhere. When a chip suddenly demands a lot of current - a burst of computation, an AI workload spinning up - the supply voltage momentarily sags. That sag can cause errors, so designers guard against it by running slower and at higher voltage than they would otherwise need. In 2023 Movellus announced what it called an industry-first integrated droop response system: circuits that detect the sag and adapt the clock in nanoseconds, reclaiming the margin that everyone else pads. It is the kind of feature that does not make a keynote slide but does show up in a benchmark.
From there the logic kept extending. If you are already sitting on the clock and watching for droop, you have a privileged view of the chip's internal state. So Aeonic Insight turned that view into a product - on-die telemetry that reports power-grid and clock health while the silicon is running, useful for post-silicon debugging and for what the industry calls silicon lifecycle management. In 2025 the company debuted PDNIQ, which it billed as an industry-first on-die power delivery network analyzer. And in 2024 Aeonic Power moved voltage regulation itself onto the die, with the company claiming up to 15% energy savings on digital cores - a meaningful number when your customer is a data center paying the electricity bill.
The origin story is almost too neat. In 2014, two electrical engineering PhD students at the University of Michigan - Mo Faisal and Jeff Fredenburg - entered a business plan competition with an idea drawn from Faisal's doctoral research on synthesizable clock generators. They won the Michigan Business Challenge. That win became a company. Faisal, who had done time at Intel and PMC Sierra, became CEO; Fredenburg provided technical vision; and their advisor, Prof. David Wentzloff, eventually joined the board. The company headquartered itself in San Jose but kept engineering centers in Michigan and Toronto, on the reasonable theory that good chip designers do not all live in one zip code.
The cap table tells you who takes this seriously. The $23 million Series B that Movellus closed in September 2022 included Intel Capital, In-Q-Tel - the strategic investment arm associated with U.S. intelligence interests - and SK hynix, the memory giant, alongside MESH, Candou Ventures, Michigan Capital Network and others. Total raised sits around $32.75 million. That is not a hyperscaler's war chest, but for an IP company that licenses the same blocks into design after design, capital efficiency is the point.
The strategy is old and durable: sell picks and shovels in a gold rush. The gold rush, at the moment, is AI silicon, and it is fundamentally constrained by power and heat. A company that makes chips run faster and cooler by owning the clock, the droop response and the power delivery is standing in exactly the right doorway. In 2024 Tenstorrent - the AI-hardware company - licensed Movellus' digital IP for its chiplet-based AI and HPC solutions, which is precisely the kind of validation an infrastructure-IP business needs: someone building the future decided the future needed your parts.
None of this is glamorous. There is no consumer to delight, no app to open, no logo on the outside of a device. Movellus operates in the layer beneath the layer, the part of the chip nobody photographs. But the unglamorous layer is often the defensible one. Clocks are hard. Droop is hard. Doing them as portable, synthesizable digital IP is harder still. And every advanced chip needs a heartbeat that keeps time - which is a good business to be in, as long as the beat goes on.