# Tabula

> Tabula was a Santa Clara fabless semiconductor startup that tried to outflank the FPGA duopoly by making one physical logic fabric behave like several virtual layers. Its Spacetime architecture, ABAX chips, and Stylus tools promised high-end programmable logic at volume prices of $105 to $200, but the business never achieved enough market traction to carry its long development cycle and more than $200 million of venture backing. The company shut down in March 2015, leaving a sharp lesson: in programmable hardware, architecture, compiler, process technology, IP, support, and customer confidence are one product.

- **Founded:** 2003
- **Headquarters:** Santa Clara, United States
- **Founders:** Steve Teig (Founder, President and CTO)
- **Products:** Spacetime architecture, ABAX 3PLD family, Stylus, ABAX2P1, 100G reference design suite
- **Notable:** Developed a production time-multiplexed FPGA architecture that presented up to eight virtual folds in ABAX and 12 in ABAX2., Named Cisco as a customer in 2011., Raised a $108 million Series D in 2011, one of the largest semiconductor venture rounds of its era.

## Products & services

- **Spacetime architecture** — A time-multiplexed programmable-logic architecture that rapidly reconfigured logic, memory, and interconnect so one physical fabric appeared as multiple virtual folds.
- **ABAX 3PLD family** — First-generation 40 nm programmable-logic devices with eight folds, a 1.6 GHz base clock, 220,000 to 630,000 virtual LUTs, 5.5 MB of user memory, and volume pricing from $105 to $200.
- **Stylus** — Integrated synthesis, timing, power analysis, debugging, and 3D place-and-route software that mapped standard VHDL, Verilog, and SystemVerilog designs onto Spacetime hardware.
- **ABAX2P1** — A second-generation 22 nm Intel-manufactured 3PLD with 12-fold Spacetime operation, up to a 2 GHz fabric clock, hardened networking functions, and reference designs for 40G and 100G packet processing.
- **100G reference design suite** — RTL, test benches, IP, and designs for 4x100G switching, bridging, search, and multiport 10 Gigabit Ethernet applications.

## Achievements

- Developed a production time-multiplexed FPGA architecture that presented up to eight virtual folds in ABAX and 12 in ABAX2.
- Named Cisco as a customer in 2011.
- Raised a $108 million Series D in 2011, one of the largest semiconductor venture rounds of its era.
- Became an early outside customer of Intel's then-new 22 nm Tri-Gate foundry process.
- Recognized in 2012 with an Edison Award, an American Business Gold Award, inclusion in MIT Technology Review's TR50, and the number-three position on The Wall Street Journal's Next Big Thing list.
- Built a patent portfolio spanning programmable architecture, EDA, interconnect, timing, and configurable storage.

## Latest updates

- **2013-03** — Introduced ABAX2P1 and a suite of programmable 100G networking reference designs built on Intel's 22 nm Tri-Gate process.
- **2014-10** — Detailed verification and timing-closure techniques intended to make the unusual Spacetime fabric behave predictably in conventional design flows.
- **2015-02** — A California filing and industry reports disclosed that the company would close, affecting about 120 jobs.
- **2015-03** — Tabula ceased operations on March 24, 2015.

## Links

- Website: http://www.tabula.com
- LinkedIn: https://www.linkedin.com/company/tabula
- Facebook: https://facebook.com/tabula.en

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Last updated: 2026-09-24