# eTopus Technology

> eTopus Technology is a San Jose-based semiconductor IP company that designs ultra-high-speed, ADC/DSP-based SerDes and die-to-die interconnect IP for data centers, high-performance computing, AI, 5G and storage. Founded in 2012 by Harry Chan and Peter Kou, the company licenses silicon-proven PHY IP - spanning 112G on advanced 6/7nm nodes down to 22nm - plus chiplet interfaces supporting UCIe, Bunch of Wires, PCIe Gen 5/6 and CXL. eTopus positions itself on low latency and low power, and has built collaborative chiplet platforms with partners including QuickLogic, OpenFive and CoMira.

- **Founded:** 2012
- **Headquarters:** San Jose, California, United States
- **Founders:** Harry Chan (Founder & CEO), Peter Kou (Co-Founder & CTO), Danfeng Xu (Co-Founder & VP, Analog)
- **Team size:** ~49 employees
- **Products:** 112G SerDes PHY IP, Ultra Low Latency 400G IP, PCIe / CXL Interconnect IP, Chiplet Interface IP (UCIe / Bunch of Wires), Disaggregated eFPGA Chiplet Template
- **Notable:** Pioneered ADC/DSP-based SerDes at 56Gbps with PAM-4 support as early as 2016., Co-announced the industry's first disaggregated, flexible eFPGA chiplet template with QuickLogic., Delivered 112G SerDes PHY IP on advanced 6/7nm nodes with adoption by Tier-1 semiconductor players.

## Products & services

- **112G SerDes PHY IP** — Ultra-high-speed ADC/DSP-based SerDes on 6nm/7nm nodes, with 56G on 16/12nm and up to 58G on 22nm.
- **Ultra Low Latency 400G IP** — Combined FEC and SerDes latency claimed well under 10ns, versus up to ~100ns per link for competing approaches.
- **PCIe / CXL Interconnect IP** — LR PCIe Gen 5, CXL 2.0/3, Gen 6 and 800G support on 7/6nm for SoC and chiplet clients (with CoMira).
- **Chiplet Interface IP (UCIe / Bunch of Wires)** — Die-to-die interface IP supporting UCIe and BoW standards for high-bandwidth chiplet integration.
- **Disaggregated eFPGA Chiplet Template** — Industry-first flexible eFPGA chiplet template with QuickLogic, built on 6nm with configurable LUT/BRAM/DSP.

## Achievements

- Pioneered ADC/DSP-based SerDes at 56Gbps with PAM-4 support as early as 2016.
- Co-announced the industry's first disaggregated, flexible eFPGA chiplet template with QuickLogic.
- Delivered 112G SerDes PHY IP on advanced 6/7nm nodes with adoption by Tier-1 semiconductor players.
- Founders and team hold roughly 80+ combined patents in mixed-signal and DSP design.

## Latest updates

- **2024-07** — Closed a Series B II round with participation from Qingzi Zeyuan Capital.
- **2023-12** — Raised a $13.75M Series B round led by Hua Capital.
- **2022-06** — Announced the disaggregated, flexible eFPGA chiplet template with QuickLogic.
- **2022-01** — Announced PCIe IP Gen 1-6 and 800G support for 7/6nm with CoMira, targeting SoC and chiplet clients.

## Links

- Website: https://etopus.com
- LinkedIn: http://www.linkedin.com/company/etopus-technology-inc.
- Twitter/X: https://twitter.com/eTopus_IO
- Facebook: https://www.facebook.com/eTopusIO/

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Profile page: https://yespress.io/etopus-technology
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Last updated: 2026-07-12